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The Understanding of Chip Reliability is now at the core of stakes in our data-driven age where business opportunities related to streamlined access to data are huge and endless.
As the chip needs to be stable at normal operating conditions, IBM semiconductor and technology researchers unveiled five papers on the technical and material advancement of its next-generation chip development, including the 7 nanometer node, at the IEEE International Reliability Physics Symposium (IRPS), April 4-6, 2017.
The paper, Time Dependent Dielectric Breakdown of SiN, SiBCN and SiOCN spacer dielectric, presents a comprehensive comparison of several materials that are used for the insulator in the space between the electrical contacts at the transistor level.
IBM’s two papers, A Stochastic Model for Impact of LER on BEOL TDDB, and A New and Holistic Modelling Approach for Impact of Line-Edge Roughness on Dielectric Reliability address ways to model LER and other forms of spacing variation to correctly anticipate voltage effects on chip reliability.
In the paper, A Process-Variation-Cognizant Efficient MOL and BEOL TDDB Evaluation Method, IBM Systems engineers from the Fabless Reliability Group, with IBM Research engineers, developed a cognitive computing technique for optimal pre-screening and test sequencing to dramatically improve the efficiency of testing.
A different reliability issue concerning the long-term threshold voltage instability of transistors is the subject of extensive research in the paper, Comparison of DC and AC NBTI Kinetics in Si and SiGe p-FinFETs.
For more information about IBM semiconductor and technology research, please visit: http://ibm.co/2oukGot